In this section we highlight some of the articles that you will find in the magazine. Each issue has new features, so be sure to check back with each release to find the latest articles.
Optimizing DDR3 Designs for Timing and Voltage Margins
Written by Todd Westerhoff
Saturday, 25 October 2008 18:03
Sisoft’s Todd Westerhoff shows how to optimize your DDR3 interface to properly account for setup and hold timing.
With many high-speed interfaces going beyond 5 Gbps traditional simulation and modeling techniques for SerDes channels are not sufficient anymore. Can the proposed IBIS-AMI specification provide the modeling framework needed to solve interoperability issues for designers?
Find out what the IBIS Quality Task Group is trying to do about quality issues in IBIS models. Mike Labonte from Cisco, chair of the IBIS Quality Task Group, covers the history of quality issues in IBIS and the new IBIS Quality Checklist.
